[6.18] Rebase ARM commits from 4.14 kernel - #286

In order to support building the tools needed for on-target versioning for
x86_64 targets (since HOSTCC continues to be x86), adding a pregenerated header
for that toolchain.

Signed-off-by: Brad Mouring <brad.mouring@ni.com>
Acked-by: Gratian Crisan <gratian.crisan@ni.com>

Signed-off-by: Ben Shelton <ben.shelton@ni.com>
Acked-by: Scot Salmon <scot.salmon@ni.com>
Acked-by: Terry Wilcox <terry.wilcox@ni.com>
Natinst-ReviewBoard-ID: 69848
[gratian: convert to new syscall table format for arm]
Signed-off-by: Gratian Crisan <gratian.crisan@ni.com>
[cvadrevu: Updated to just add missing Zynq code]
Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

On systems where FPGA autoload is controlled by software, we need a way
to determine if a system has just had power applied. This is necessary
to implement the autoload on every power-on feature. Once the FPGA has
been autloaded after power-on, software sets a bit in the CPLD so that
subsequent (non power-on) resets don't cause the FPGA to be autoloaded
again. The CPLD provides the HARD_BOOT_N bit for this purpose.

On systems where FPGA autoload is controlled by hardware, such as Smasher,
we need to set this bit at some point after power-on so that software can
correctly determine the reset state of the controller. Since software has
no insight into the status of FPGA autoload on these systems, we can just
set this bit if necessary when the driver loads.

Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>
[cvadrevu: Fixed trivial conflicts with
  91d93a7 ("nirtfeatures: Only register bi-color LEDs on supported targets")]
  6c83dd7 ("nirtfeatures: Added NI RT features driver")]
Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

The BIOS will set the HARD_BOOT_N bit at post, so the driver no longer
needs to do this.

Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>
[cvadrevu: Fixed trivial conflicts with
  91d93a7: ("nirtfeatures: Only register bi-color LEDs on supported targets")
  f3ab444: ("nirtfeatures: Use managed resource allocation")]
Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

Add documentation for leds-ni793x devicetree bindings. This driver controls
the RT User1 LED on the FlexRIO NI-793xR devices.

Signed-off-by: Francesca Ramadori <francesca.ramadori@ni.com>
Signed-off-by: Brad Mouring <brad.mouring@ni.com>
Acked-by: Josh Cartwright <joshc@ni.com>
Acked-by: Ben Shelton <ben.shelton@ni.com>

Clients are drivers for peripherals with physical lines routed through
the FPGA.  Ethernet and serial will want to receive notifications so
they can avoid accessing hardware while the FPGA is unprogrammed.

Signed-off-by: Kyle Teske <kyle.teske@ni.com>
Natinst-ReviewBoard-ID: 26536
[cvadrevu: Fixed trivial conflicts due to newer modules]
Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

We add a separate notification which will get called when FPGA
programming fails. This is to enable client drivers to know when to stop
waiting for FPGA to come up, if the re-programming fails.

Signed-off-by: Karthik Manamcheri <karthik.manamcheri@ni.com>

If fpgaperipheral_probe succeeds, it generates no debug output, even at
the highest loglevel.  Add a success message to make device tree
debugging easier.

Signed-off-by: Ben Shelton <ben.shelton@ni.com>

This is a snapshot of the Xilinx-provided PL353 NAND driver as of commit
3fa059c ("nand: pl353: Renamed
zynq_nand driver as pl353_nand").

The original driver author is Punnaiah Choudary Kalluri <punnaia@xilinx.com>.

Signed-off-by: Josh Cartwright <joshc@ni.com>
[cvadrevu: Fixed trivial conflicts due to newer modules]
Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

The default 3.10 NAND driver does not support subpage reads or writes
for our device, which causes it not to play nicely with partitions that
have already been formatted with this support.

This commit forward-ports the following commits to enable this feature:

 - NAND: Added subpage read support for on-die ECC devices using Xilinx PS
NAND controller.
 - Zynq NAND: Fixed block erase timeout problem and off-by-one math error
 - Zynq NAND: Subpage write support.

Acked-by: Jeff Westfahl <jeff.westfahl@ni.com>
Signed-off-by: Ben Shelton <ben.shelton@ni.com>

Replace the NAND READ0 command with an RNDOUT command if the READ0 is for
the most recently read page and no other command has been sent to the NAND
that would make another READ0 necessary.

Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>

When using on-die ECC, check the NAND status after READ0 operations for an
ECC warning or error.

Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>

In some cases, CS remains asserted to the NAND chip after an operation has
completed. We should make sure to deassert CS when the chip is no longer
in use.

Refactored to avoid variable hiding.

Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>

The Zynq static memory controller is based on ARM PL353. The following commit
[3fa059c nand: pl353: Renamed zynq_nand driver as pl353_nand]
renamed the driver to "pl353-nand" to match the hardware. This creates problems
on shipping hardware due to a mismatch between what u-boot expects
(via bootargs/mtdparts) and the kernel driver name. This commit reverts the
NAND driver name to the old "xilinx_nand" in order to preserve compatibility.

Signed-off-by: Gratian Crisan <gratian.crisan@ni.com>
Acked-by: Joseph Hershberger <joseph.hershberger@ni.com>
Acked-by: Terry Wilcox <terry.wilcox@ni.com>
Natinst-ReviewBoard-ID: 79256

In ed4f85c (mtd: nand: embed an mtd_info structure into nand_chip),
an mtd_info structure was embedded into the nand_chip struct
since all drivers were doing the same thing. This was an attempt
to simplify and streamline.

In 862eba5 (mtd: nand: make use of mtd_to_nand() in NAND core code)
this change was put into practice, changing the nand_core's mapping
of mtd-to-nand to use the embedded mtd_info in the nand_chip struct.

Update the pl353_nand driver to use this new embedded structure.

Signed-off-by: Brad Mouring <brad.mouring@ni.com>

Add `enable_subpage_read` and `enable_subpage_write` load-time options
to toggle subpage read/write operations on pl353 chips. Both options are
enabled by default, and may be toggled in the boot loader.

Signed-off-by: Haris Okanovic <haris.okanovic@ni.com>
Acked-by: Gratian Crisan <gratian.crisan@ni.com>
Acked-by: Jeff Westfahl <jeff.westfahl@ni.com>

Natinst-CAR-ID: 599280
Natinst-ReviewBoard-ID: 151758
(cherry picked from commit 311a5711cfdbfa20e3f4ec2dbd429f96b9f76c2f)

Add dsb(st) [1] after writes to command register to ensure the chip
receives them before ndelay()-ing to synchronize driver/chip state.

The subsequent ndelay()s (after dsb(st)) gives the chip enough time to
process "quick" commands (like RNDOUT) which don't change status flags
or issue interrupts upon completion. They are assumed to complete at
most 100ns after delivery on the bus. It's therefore critical to ensure
they make it all the way down to the chip before the driver ndelay()s
for on-chip processing. Otherwise, commands may get buffered in the
interconnect between the CPU and chip while the driver waits. Subsequent
read/write operations may then be delivered inside the on-chip
processing window resulting in incorrect behavior.

In particular, a READ0 (page select + col change), followed by RNDOUT
(column change only), followed by data reads <1page in size results in
sporadic one-byte data corruption, particularity when the bus is busy.

Testing:

No longer see a sporadic 1 byte corruption after RNDOUT by repeatedly
reading the entire Linux file system after fs-cache drop for 48 hours.

Verified RNDOUT requires the ndelay() by unsuccessfully attempting to
remove it for that command. Doing so results in the same sporadic 1 byte
corruption in the aforementioned read test.

Ran fio [2] with random read/write+verify for 48 hours; no corruptions
reported. Config: rw=randrw, size=100M, bs=5k, verify=sha256, numjobs=5

Hardware:
 National Instruments cRIO-9068 [3]
  Xilinx Zynq-7020 SoC
  MT29F8G08ADBDAH4 8GB NAND

[1] http://infocenter.arm.com/help/topic/com.arm.doc.dui0489c/CIHGHHIE.html#id4692433
[2] http://linux.die.net/man/1/fio
[3] https://sine.ni.com/nips/cds/view/p/lang/en/nid/211620

Signed-off-by: Haris Okanovic <haris.okanovic@ni.com>
Signed-off-by: Brad Mouring <brad.mouring@ni.com>
Acked-by: Jeff Westfahl <jeff.westfahl@ni.com>
Natinst-CAR-ID: 599280
Natinst-ReviewBoard-ID: 152950

Haven't yet figured out why this is required...hack it.

Signed-off-by: Josh Cartwright <joshc@ni.com>

Commit aab616e ("mtd: kill the nand_ecclayout struct") removed the
nand_ecclayout struct. Convert the pl353_nand driver to the new
mtd_ooblayout_ops model.

Fixes: 627a2ef8fb01 ("mtd: nand: pl353: add snapshot of driver from
linux-xlnx tree")

Signed-off-by: Gratian Crisan <gratian.crisan@ni.com>

Commit 7f2b092 ("mtd: nand: kill the ecc->layout field") removed
direct access to the ecc layout field. Use instead the mtd_ooblayout_xxx()
helper functions in places where the eccpos[] array was accessed directly.

Fixes: 627a2ef8fb01 ("mtd: nand: pl353: add snapshot of driver from
linux-xlnx tree")

Signed-off-by: Gratian Crisan <gratian.crisan@ni.com>

The NI Zynq prototype board has a CPLD that provides various
board-management capabilities.

Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Signed-off-by: Jaeden Amero <jaeden.amero@ni.com>
Acked-by: Jeff Westfahl <jeff.westfahl@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
[cvadrevu: Fixed trivial conflicts due to newer module]
Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

This provides a general purpose, raw interface to the CPLD's scratchpad.
The scratchpad can be used to communicate between soft reboots of the
target.

Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>

This is a read/write attribute that will set the necessary bits in the
scratch registers used to determine which mode the board boots into.
Currently, valid modes are 'runtime', 'safemode', and 'recovery'.

Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>

Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Signed-off-by: Scot Salmon <scot.salmon@ni.com>
Acked-by: Brad Mouring <brad.mouring@ni.com>
Acked-by: Josh Cartwright <josh.cartwright@ni.com>
Natinst-ReviewBoard-ID: 36482

Use the SLCR to reboot the zynq if a reset function is not provided.

Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>
Acked-by: Jeff Westfahl <jeff.westfahl@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Natinst-ReviewBoard-ID: 90458

With the Baytrail SD controllers on cRIO-905x, we can run into two
conditions which cause functional problems with the NI-recommended microSD
card. The first is a runt pulse after SD card clock disable, which is fixed
by using SDHCI_QUIRK2_NEED_DELAY_AFTER_CLK_DISABLE to wait after disabling
the clock. The second is receiving two SDHCI_INT_CARD_INSERT interrupts,
which causes us to set up the card twice a make our recommended microSD
card unresponsive. Work around this by using
SDHCI_QUIRK2_SPURIOUS_CARD_INSERT_INTERRUPT.

Signed-off-by: Kyle Roeschley <kyle.roeschley@ni.com>
Signed-off-by: Brad Mouring <brad.mouring@ni.com>
Acked-by: Tony Liechty <tony.liechty@ni.com>
Acked-by: Nathan Sullivan <nathan.sullivan@ni.com>
Natinst-ReviewBoard-ID: 236135
Natinst-CAR-ID: 696865
Natinst-CAR-ID: 694815

By default, the interrupt output of the Marvell 88E1512 PHY is
configured as an LED output, and is driven low. If we have a case where
eth1 is brought up before eth0, this causes an interrupt storm, and
Linux eventually gives up and disables the PHY interrupt line. Adding a
probe function to the Marvell 88E1512 PHY driver and moving the
interrupt output configuration there resolves this problem.

[bm: Adjust for d2fa47d 'phy: marvell: Add ethtool statistics counters']

Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>
Signed-off-by: Mihaly Varga <mihaly.varga@ni.com>
Acked-by: Brad Mouring <brad.mouring@ni.com>
Acked-by: Ben Shelton <ben.shelton@ni.com>
Acked-by: Jaeden Amero <jaeden.amero@ni.com>
Natinst-ReviewBoard-ID: 81627

[bm: Restore correct page on LED/irq config]
Signed-off-by: Brad Mouring <brad.mouring@ni.com>
Acked-by: Jeff Westfahl <jeff.westfahl@ni.com>
Natinst-ReviewBoard-ID: 148255

[gratian: split LED pin setup from m88e151x_probe; fixes conflict with 0b04680 ("phy: marvell: Add support for temperature sensor")]
Signed-off-by: Gratian Crisan <gratian.crisan@ni.com>
[cvadrevu: Fixed trivial conflict with b697d9d ("net: phy: marvell: add SFP support for 88E1510")]
[cvadrevu: Updated marvell_get_page to marvell_read_page due to 424ca4c ("net: phy: marvell: fix paged access races")]
Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

Upstream removed spin lock usage in the set_ios path with commit
d1e4f74 ("mmc: sdhci: Do not use spin lock in set_ios paths"), which
means that our calls to spin_(un)lock_irq() in sdhci_set_clock() now cause
an error on boot if a card is not present or a crash if one is present.
Remove these calls so we don't do that and to match upstream's change.

Fixes: 815777e ("mmc: sdhci: Add quirk for delay between clock disable and param change")
Fixes: 30d2f45 ("mmc: sdhci: Add quirk work around double rescan")

Signed-off-by: Kyle Roeschley <kyle.roeschley@ni.com>
Acked-by: Gratian Crisan <gratian.crisan@ni.com>
Acked-by: Brandon Streiff <brandon.streiff@ni.com>
Natinst-ReviewBoard-ID: 264712
Natinst-CAR-ID: 720310

NI roboRIO 2.0 has relocated the clock pin from 1.8V bank to 3.3V bank.
Hence, it required to update both product and supported version to indicate the changes in HW.

Signed-off-by: Kim Khiam Lim <kim.khiam.lim@ni.com>

Import the NI Zynq board device trees from the 4.14 kernel and add them
to the Xilinx DTB build list.

Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

These have been superceded by ni-<devicecode>.dts.

Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

The NI device trees were copied from the 4.14 kernel and still reopen
SoC nodes using their old names and hierarchy.  The current Zynq device
tree defines these nodes with labels and uses gpio0 for the GPIO
controller.

Convert the NI board files to extend the existing amba, I2C, SPI, and
ADC nodes through label references.  Update GPIO references from gpio to
gpio0 and move the myRIO I2C and SPI configuration to the corresponding
labeled nodes.

This allows the NI Zynq device trees to compile against the current
zynq-7000.dtsi.

Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

Set the address and size cells on the NAND controller so the nand@0 reg
property is parsed correctly.

Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

The CoreSight blocks are not accessible on NI Zynq targets. Reading
their AMBA identification registers hangs the SoC before any driver
binds.

Disable the nodes to allow the system to boot.

Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

phy_start_interrupts, phy_stop_interrupts have been removed in newer
kernel. Replace them with phy_request_interrupt, phy_free_interrupt.

Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

Drop the unused device ID argument from probe and change remove to
return void, matching the current I2C driver callback signatures.

Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

UPF_IOREMAP defers mapping the register resource until the serial port
is started.  The NI 16550 driver accesses registers during probe to
determine FIFO sizes and configure the PMR, before the port has been
started.

Map the MMIO resource with devm_ioremap() during probe and assign the
result to port->membase so these early register accesses use a valid
mapping.

Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

Port this change from commit [1] for nati_x86_64_defconfig.

NILRT is currently booted with `rcu_nocbs=all` kernel parameter set.
Enable CONFIG_RCU_NOCB_CPU_DEFAULT_ALL which will allow us to remove
the boot option in the future.

Note that it is still possible to override this option using rcu_nocbs
or nohz_full boot parameters.

[1]: 4d93b1f ("nati_x86_64_defconfig: enable CONFIG_RCU_NOCB_CPU_DEFAULT_ALL")

Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

Ported from 4.14 and updated to work on 6.18 kernel.

Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

Do not re-initialize maybe active work in the function the work
handler will call.

fixes: 8f9d74e ("net/phy: micrel: Fix workaround for autoneg failure")
Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>

Added support for an EMIO GPIO for telling the GMII-RGMII conversion
logic in the PL what the link speed is. This is necessary for 1Gb
Ethernet to work on many NI targets.

These changes also magically fix the secondary Ethernet speed LED.

Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>
Signed-off-by: Jaeden Amero <jaeden.amero@ni.com>
Acked-by: Ben Shelton <ben.shelton@ni.com>
Acked-by: Gratian Crisan <gratian.crisan@ni.com>
Natinst-ReviewBoard-ID: 84563
(joshc: updated to use gpiod_* APIs)
(bm: update to gpiod_* APIs)
Signed-off-by: Josh Cartwright <joshc@ni.com>
[cvadrevu: Port link-speed GPIO handling to phylink callbacks, add the
           GPIO consumer include, and fix probe error-path cleanup]
Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>

Install the ARM cross-compiler and U-Boot tools, build and validate
Zynq, Bluefin, and SLSC defconfigs. Use separate output
directories for all platform builds to avoid artifact conflicts.

Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>